This invention relates to a programmable controller and more particularly to a controller having master and slave Central Processing Units (hereinafter referred to as CPU).
An example of a typical sequence program programmed by a ladder diagram is shown in FIG. 1. A system diagram of a typical programmable controller (hereinafter referred to as PC) is shown in FIG. 2. For PC programming and execution monitoring, a programmable controller having a graphic display corresponding to FIG. 1 is used.
In the graphic display, contacts or coils in the ON state are displayed by means of higher brightness, or by means of a colour change. Also, the path through which the current passes from the left bus to the right-end coil is indicated by increased brightness, so that the state of command execution and/or condition under which output is obtained can be ascertained visually.
To achieve this graphic representation, every time a command is executed, the ON/OFF information of the operand devices(relays and coils) that are used for executing that command, and the ON/OFF information of the output, which is determined by the input to these commands and the state of devices, must be accumulated by the CPU.
When these items of bit data are stored in the PC memory, to increase the efficiency of memory usage, they are stored in order of bit units, from the head of the word.
The aforesaid processing is executed by software of the CPU. However, in an ordinary CPU there are no bit operation commands, so these must be realized by a combination of shift processing and logic calculation. This processing is therefore fairly complex, as shown by the flow-chart of FIG. 3. In particular, the number of calculation steps becomes large on moving to the next word when the memory of one word becomes full. Also, since this processing is performed every time a command is executed, program execution during monitoring becomes appreciably slower than what it is when monitoring is not performed.
Recently, PCs have been required to have increasingly high data processing capability, numerical calculation capability and high sequence calculation processing capability. However, ordinary CPUs, although they are fast with numerical and data calculation, are slow at execution of sequence commands. As a result, processing time can be shortened by using a special purpose CPU for sequence calculation.
PCs have therefore appeared wherein processing is shared between a master CPU, for executing the operating system program and for processing of numerical data, and a slave CPU for executing sequence programs, such as those realized by the ladder diagram. These CPUs are used under time sharing, as required.
However, in monitoring, even in such a PC, the slave CPU interrupts the master CPU to make it read the ON/OFF information of the executed command output and of the devices corresponding to each command.
Consequently, when monitoring is performed, the execution speed is markedly lower.